module top;
wire A, B, C, D, NA, NB, NC, ND, NF, F1, F2, F3, F4, F5, F6, F;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);
nor a1(NA, A, A);
nor a2(NB, B, B);
nor a3(NC, C, C);
nor a4(ND, D, D);
nor r1(F1,A,B,NC);
nor r2(F2,A,NC,D);
nor r3(F3,B,NC,D);
nor r4(F4,NB,C,ND);
nor r5(F5,NA,C,ND);
nor r6(F6,NA,NB,ND);
nor r7(NF,F1,F2,F3,F4,F5,F6);
nor r8(F,NF,NF);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
begin
#(PERIOD/2) clk=~clk;
end
always@(posedge clk)
if($time>1000)$stop;
endmodule
