上機考 NOR

module top;

wire A, B, C, D, NA, NB, NC, ND, NF, F1, F2, F3, F4, F5, F6, F;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);

nor a1(NA, A, A);
nor a2(NB, B, B);
nor a3(NC, C, C);
nor a4(ND, D, D);
nor r1(F1,A,B,NC);
nor r2(F2,A,NC,D);
nor r3(F3,B,NC,D);
nor r4(F4,NB,C,ND);
nor r5(F5,NA,C,ND);
nor r6(F6,NA,NB,ND);
nor r7(NF,F1,F2,F3,F4,F5,F6);
nor r8(F,NF,NF);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

三位元加法器結構

adder1 M1(Cin,A1,B1,A2,B2,A3,B3,Cout1,Cout2,Cout3,Sum1,Sum2,Sum3);
endmodule

module adder1(Cin,A1,B1,A2,B2,A3,B3,Cout1,Cout2,Cout3,Sum1,Sum2,Sum3);
output Cout1,Sum1,Cout2,Cout3,Sum2,Sum3;
input A1,B1,A2,B2,A3,B3,Cin;
and I1 (A1andB1, A1, B1);
xor I2 (A1xorB1, A1, B1);
and I3 (And1, A1xorB1, Cin);
or I4 (Cout1, A1andB1, And1);
xor I5 (Sum1, A1xorB1, Cin);

and I6 (A2andB2, A2, B2);
xor I7 (A2xorB2, A2, B2);
and I8 (And2, A2xorB2, Cout1);
or I9 (Cout2, A2andB2, And2);
xor I10 (Sum2, A2xorB2, Cout1);


and I11 (A3andB3, A3, B3);
xor I12 (A3xorB3, A3, B2);
and I13 (And3, A3xorB3, Cout2);
or I14 (Cout3, A3andB3, And3);
xor I15 (Sum3, A3xorB3, Cout2);
endmodule

一位元全加法器

and a1(Z1, A, B);

xor a2(Z2, A, B);

and a3(Z3, Z2, Cin);

or a4(Cout, Z1,Z3);

xor a5(Sum, Cin,Z2);

一&二位元

一位元

                                                                          二位元

3bit多工器，不太會做QQ

多工邏輯閘2

真值表

多工 邏輯閘1

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