三位元加法器結構

adder1 M1(Cin,A1,B1,A2,B2,A3,B3,Cout1,Cout2,Cout3,Sum1,Sum2,Sum3);
endmodule

module adder1(Cin,A1,B1,A2,B2,A3,B3,Cout1,Cout2,Cout3,Sum1,Sum2,Sum3);
output Cout1,Sum1,Cout2,Cout3,Sum2,Sum3;
input A1,B1,A2,B2,A3,B3,Cin;
and I1 (A1andB1, A1, B1);
xor I2 (A1xorB1, A1, B1);
and I3 (And1, A1xorB1, Cin);
or I4 (Cout1, A1andB1, And1);
xor I5 (Sum1, A1xorB1, Cin);

and I6 (A2andB2, A2, B2);
xor I7 (A2xorB2, A2, B2);
and I8 (And2, A2xorB2, Cout1);
or I9 (Cout2, A2andB2, And2);
xor I10 (Sum2, A2xorB2, Cout1);


and I11 (A3andB3, A3, B3);
xor I12 (A3xorB3, A3, B2);
and I13 (And3, A3xorB3, Cout2);
or I14 (Cout3, A3andB3, And3);
xor I15 (Sum3, A3xorB3, Cout2);
endmodule

一位元全加法器

and a1(Z1, A, B);

xor a2(Z2, A, B);

and a3(Z3, Z2, Cin);

or a4(Cout, Z1,Z3);

xor a5(Sum, Cin,Z2);

一&二位元

一位元

                                                                          二位元

3bit多工器，不太會做QQ

多工邏輯閘2

真值表

多工 邏輯閘1

補交上禮拜作業

module top;

wire A, B, C, OUT1, OUT2;

system_clock #400 clock1(A);

system_clock #200 clock2(B);

system_clock #100 clock3(C);

and a1(OUT1, A, B);

and a2(OUT2, OUT1, C);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

 begin

#(PERIOD/2) clk=~clk;

 end

always@(posedge clk)

 if($time>1000)$stop;

endmodule

今天上課學到and邏輯閘的應用概念

雖然不太會((被打

但是會努力的