module top;

wire A, B, C, OUT1, OUT2;

system_clock #400 clock1(A);

system_clock #200 clock2(B);

system_clock #100 clock3(C);

and a1(OUT1, A, B);

and a2(OUT2, OUT1, C);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

 begin

#(PERIOD/2) clk=~clk;

 end

always@(posedge clk)

 if($time>1000)$stop;

endmodule

今天上課學到and邏輯閘的應用概念

雖然不太會((被打

但是會努力的